Offer summary
Qualifications:
Masters Degree in Electrical Engineering, Computer Science or equivalent, 6+ years of relevant work experience, Deep hardware engineering background in VLSI or Computer Architecture, Experience with Verilog, System Verilog, or similar HVL, Knowledge of CAD and physical design methodologies.
Key responsabilities:
- Develop and optimize floorplans during chip development
- Drive area review process and collaborate with ASIC design team
- Solve timing and routing congestion issues
- Build tools and improve infrastructure for optimization