SoC Logic Design Engineer

Job Details:

Job Description:

Altera is looking for a SoC/Solution SoC front-end design engineer for FPGA products. This forward-looking dynamic role provides unique opportunities to influence future product roadmap, requiring a self-starter with strong personal communication and collaboration skills.

The successful incumbent in this position will perform the following but not limited to:

• Work with cross functional teams and define Micro-architecture specifications for the FPGA solutions
• Collaborate with internal and external team members on architectural decisions, development flows and methodologies.
• Perform feasibility study on different third-party IP and integrate IP at the SOC level.
• RTL Design and implementation of Soft IP blocks and SoC solutions.
• Run Lint, CDC, Synthesis, STA and formal verification tools, work closely with Backend team on floorplan, Constraints definition and timing analysis.
• Closely work with Verification team and help define test plan and debug design.
• Participate in design reviews of hardware and related software systems.
• Participate and drive timing convergence for high-speed designs including micro-architecture optimizations

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirements:
Bachelor's degree in computer engineering, electrical Engineering or related field.

Minimum Qualifications

7+ years of relevant experience in the following areas:

• Experience with CPU based SoC designs processor based SoC architectures.
• Experience with NoC design and integration with AMBA interconnect protocols
• Working experience with peripheral IPs such as USB, Ethernet, I3C.
• RTL developer using ASIC development techniques and designs flows at modern technology nodes including synthesis and timing closure
• Understanding of clock, debug, security, low power methodologies at the SoC level. 
• Digital Design experience
• Experience with scripting languages (e.g., Python or Perl).

Preferred Requirements:

• Master's degree in computer engineering, Electrical Engineering or related field.
• 6+ years of experience in the following areas:
• Digital design involving multiple clock domains and clock, power management.
• Low power design, tools and methodologies. Power intent UPF specifications.

Job Type:

Shift:

Primary Location:

Additional Locations:

Posting Statement: