Offer summary
Qualifications:
Bachelor's or Master's degree in Engineering, Minimum 4 years of project experience, Proficient in VHDL and Verilog, Experience with Mentor ModelSim/QuestaSim, Scripting language experience, e.g., TCL.Key responsabilities:
- Requirements-based Digital Hardware Design Verification
- Formal Requirements Capture and Documentation
- Module Level Verification and Integration
- Development of Verification Cases and Test Environment
- Performing Verification and Documenting Results