Offer summary

Qualifications:

Extensive experience in power analysis and optimization is required., 10+ years of ASIC design or related work experience is essential., Proficiency in scripting languages such as Tcl and Python is necessary., Strong analytical, problem-solving, and communication skills are important. .

Key responsibilities:

Drive power analysis and projections for the development of CPUSS with an emphasis on power analysis.

Define the power vector plan for comprehensive coverage of the CPUSS.

Collaborate with RTL design, synthesis, and physical design teams to measure and optimize power.

Evaluate and propose new power optimization techniques at various design stages.

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better.

This is a CPU tech-leadership role focused on driving power analysis and projections for the development of CPUSS with an emphasis on power analysis. The role involves defining CPU rail planning and PMIC inductor sizing while collaborating closely with SoC and Board teams. Responsibilities include optimizing the system PDN for CPU rails, and managing the power vector plan for comprehensive coverage of the CPUSS. The position requires driving power analysis on RTL and Netlist using tools like Joules and PTPX, working with RTL design, synthesis, and physical design teams to measure and optimize power, and evaluating new power optimization techniques at various design stages. Additionally, the role involves tabulating metrics results for analysis comparison and working with post-silicon teams to correlate projections with silicon power measurements.

This role is Remote, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

Drive Power analysis and Projections on a project involved in the development of CPUSS with emphasis in power analysis.
Responsible for Power vector plan and definition for comprehensive coverage of the CPUSS.
Drive power analysis on RTL and Netlist using tools like Joules and PTPX.
Work closely with RTL design, Synthesis, and physical design teams to measure and optimize power.
Evaluate and propose new power optimization techniques at RTL, Synthesis and Physical Design Stages.
Tabulate metrics results for analysis comparison.
Work with post-Silicon teams to correlate projections with silicon power measurements.
Scripting in an interpreted language, minimum TCL in addition to at least one other

Experience & Qualifications:

Extensive experience in Power analysis and optimization required.
10+ years of ASIC design, or related work experience.
Experience with low power implementation techniques in RTL, Synthesis or Physical design stages.
Proficiency in scripting language, such as: Tcl, Python.
Strong analytical and problem-solving skills.
Outstanding written and verbal communication skills.
Low power intent concepts and languages (UPF or CPF).
Good understanding of Verilog/System Verilog.
Experience with CPU micro-architecture and their power challenges.
Experience in Thermal analysis.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

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