3-6+ years of industry experience in mixed signal CMOS circuit design., Hands-on experience with 2-3 analog circuit design IP from SPEC to final GDS delivery., Proficiency in CAD tools for simulation and verification., Knowledge of layout issues, particularly in FinFet nodes..
Key responsibilities:
Design CMOS/FinFet based analog and mixed signal integrated circuits.
Support analog/mixed signal IP validation from pre-layout to post-tapeout phase.
Document design ideas and simulation results according to design guidelines.
Create and update analog behavioral models using WREAL/Verilog AMS.
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