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Principal DFT Engineer


Offer summary

Qualifications:

Senior-level expertise in DFT engineering., Proficiency in SystemVerilog RTL, TCL, Python, and Unix/Linux., Knowledge of hierarchical scan, ATPG, Memory BIST., Familiarity with Siemens, Cadence, or Synopsys DFT tools..

Key responsabilities:

  • Develop and implement DFT strategies for SoCs.
  • Collaborate with cross-functional teams for test solutions.
Axelera AI logo
Axelera AI Scaleup https://axelera.ai/
51 - 200 Employees
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Job description

About Us

Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just three years, we have raised a total of $120 million and have built a world-class team of 180+ employees (including 55+ PhDs with more than 40,000 citations), both remotely from 11 different countries and with offices in Belgium, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.

We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.

Our unwavering commitment to innovation has firmly established us as a global industry pioneer. 

Are you up for the challenge?

Position Overview

Join a leading European semiconductor start-up, as a Design for Test (DFT) Engineer. Play a pivotal role in architecting and implementing innovative testability solutions for our multicore in-memory-compute SoC. This is an opportunity to contribute to cutting-edge semiconductor advancements in a collaborative and dynamic environment.

Key responsibilities:

  • Develop and implement DFT strategies for multicore in-memory-compute SoCs.

  • Collaborate with cross-functional teams to ensure seamless integration of test solutions.

  • Drive innovation by advancing testability methodologies and infrastructure.

Qualifications:

  • Experience: Senior-level expertise in DFT engineering.

  • Skills: Proficiency in SystemVerilog RTL, TCL, Python, and Unix/Linux.

  • Core Knowledge: Hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, and gate-level verification.

  • Tools: Familiarity with Siemens, Cadence, or Synopsys DFT tools.

  • Additional Expertise (a plus): IEEE standards (1149, 1500, 1687), synthesis flow, timing analysis, and Siemens DFT tools.

  • Strong problem-solving abilities, effective communication skills, and a passion for innovation in the semiconductor industry.

Location

We offer a flexible working arrangement, with options to:

  • Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity.

  • Work fully remotely from any European country (incl. the UK) you are already in.

  • Relocate with us and work from Amsterdam or Eindhoven (Netherlands) or Florence (Italy).

What we offer 

This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.   

An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team. 

At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.

Required profile

Experience

Spoken language(s):
English
Check out the description to know which languages are mandatory.

Other Skills

  • Communication
  • Problem Solving

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